ESSERC

Alternating Bit-Line 3D-DRAM Architecture for Reduced Inter-Bit-Line Coupling

Woohyun Lee*, Munhyeon Kim*, Junhyeok Kim, Jae-Joon Kim

D3TA: 38.9TOPS/W Transformer Accelerator with Dual-Port 3T-eDRAM Digital Compute-In-Memory Using HyperAttention and Triple-Sparsity-Handling

Donghyuk Kim, In-Jun Jung, Geonwoo Ko, Seri Ham, Cuong Duong Manh, Gyeongrok Yang, Joo-Young Kim

A 1.22fJ/cycle 17T Pseudo-Static True Single-Phase Clock Flip-Flop in 14nm FinFET CMOS

D. Lee, S. Kim, M. Kang, S. Jang, S. Park, J. Kim, and D. Jeon

DPIM: A 19.36TOPS/W 2T1C eDRAM Transformer-in-Memory Chip with Sparsity-Aware Quantization and Heterogeneous Dense-Sparse Core

Donghyuk Kim, Jae-Young Kim, Hyunjun Cho, Seungjae Yoo, Sukjin Lee, Sungwoong Yune, Hoichang Jeong, Keonhee Park, Ki-soo Lee, Jongchan Lee, Chanheum Han, Gunmo Koo, Yuli Han, Jaejin Kim, Jaemin Kim, Kyuho Lee, Joo-Hyung Chae, Kunhee Cho,...

Picasso: A 28nm 4.96 TOPS/W End-to-End Diffusion Accelerator with Reconfigurable Hyper-Precision and Unified Non-Matrix Processing Engine

Sungyeob Yoo, Geonwoo Ko, Seri Ham, Seeyeon Kim, Yi Chen, Joo-Young Kim